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cheshire
Verilog

cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

by pulp-platform · GitHub
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Verilog
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asicfpgariscvVerilog
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In plain words

Build a simple computer system that can run Linux using a specific chip design.

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355354
2026-07-202026-08-31
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📄 About

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

cheshire has 354 stars on GitHub. It has been forked 113 times. cheshire is written mainly in Verilog. It has been in active development since 2022. Its main topics are asic, fpga, riscv, rtl-design.

Frequently asked questions

What is cheshire?

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Is cheshire open source?

cheshire is an open-source project.

Is cheshire free?

Yes. cheshire is free and open source — you can use, modify and self-host it.

What language is cheshire written in?

cheshire is written mainly in Verilog.

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